Components

"""A simple PDK component with @pcell.

The `@pcell` decorator turns a function into a parametrized cell
factory. Each unique combination of non-default arguments yields a
distinct cell name automatically — distinct calls don't collide in GDS,
identical calls share the same cell definition under the hood.
"""
import lumicron as lm
import lumicron_pdk as lpdk

LAYER = lpdk.LayerTable(
    MTL1 = lpdk.Layer(4, 0, color="#ffd700", min_width=1.0, min_spacing=1.0),
)


@lm.pcell
def Pad(size: float = 80.0, layer: lm.LayerSpec = LAYER.MTL1):
    """A square electrical bond pad with one electrical port."""
    c = lm.CELL("Pad")

    body = lm.Rectangle(x_dim=size, y_dim=size, layer=layer)
    h = c.add(body)
    c.Place(h).at((0, 0))

    # Publish a port at the south edge so routes can land on it.
    c.add(lm.PORT(
        "p", position=(0, -size / 2), direction=270,
        width=size, layer=layer, port_type="electrical",
    ))
    return c


@lm.pcell
def PadDemo():
    """Two pads side-by-side at different sizes — different cell names auto-derived."""
    c = lm.CELL("PadDemo")
    p1 = c.add(Pad(size=80))
    p2 = c.add(Pad(size=120))
    c.Place(p1).at((0, 0))
    c.Place(p2).at((250, 0))
    return c


if __name__ == "__main__":
    PadDemo().to_gds("pad_demo.gds")

"""A component publishing ports with an attached route profile.

The trick that makes a well-curated PDK feel effortless: every
component publishes ports that already know their cross-section. End
users call ``c.Route(a.ports["o1"], b.ports["i1"])`` with no kwargs and
the route automatically stamps the right layers, claddings, and
periodic features.
"""
import lumicron as lm
import lumicron_pdk as lpdk

LAYER = lpdk.LayerTable(
    SILC = lpdk.Layer(9, 0, color="#008000", min_width=0.2, min_radius=5.0),
    OXID = lpdk.Layer(1, 0, color="#87ceeb"),
)


@lpdk.route_profile(port_width=0.5, radius=10.0, radius_min=5.0)
def silc_strip(p):
    p.layer(LAYER.SILC, width=p.port_width)
    p.layer(LAYER.OXID, width=p.port_width + 4.0)


@lm.pcell
def EdgeCouplerSi(length: float = 100.0, tip_width: float = 0.1):
    """A linear taper from a 0.1 µm tip to a 0.5 µm body, with an
    OXID cladding region around it. The output port carries
    `silc_strip` so any route off it inherits the profile."""
    c = lm.CELL("EdgeCouplerSi")

    # The taper polygon: tip → body, 4 vertices.
    body_w = 0.5
    taper = lm.Polygon(
        vertices=[
            (0, -tip_width / 2),
            (length, -body_w / 2),
            (length, body_w / 2),
            (0, tip_width / 2),
        ],
        layer=LAYER.SILC,
    )
    c.add(taper)
    c.Place(taper).at((0, 0))

    # OXID cladding rectangle hugging the taper.
    clad = lm.Rectangle(x_dim=length, y_dim=body_w + 4, layer=LAYER.OXID)
    h = c.add(clad)
    c.Place(h).using("SW").at((0, -(body_w + 4) / 2))

    # Tip port (incoming from chip edge) and body port (publishes profile).
    c.add(lm.PORT("o_tip", position=(0, 0), direction=180,
                  width=tip_width, layer=LAYER.SILC))
    c.add(lm.PORT("o1", position=(length, 0), direction=0,
                  width=body_w, route_profile=silc_strip))
    return c


@lm.pcell
def CouplerDemo():
    c = lm.CELL("CouplerDemo")
    cpl = c.add(EdgeCouplerSi(length=100))
    c.Place(cpl).at((0, 0))

    # Publish a destination port on the chip and route from coupler.o1.
    # No `radius=` / `profile=` — both come from the port's profile.
    c.add(lm.PORT("out", position=(500, 100), direction=180,
                  route_profile=silc_strip))
    c.Route(cpl.ports["o1"], c.ports["out"])
    return c


if __name__ == "__main__":
    CouplerDemo().to_gds("coupler_demo.gds")

c.add(lm.PORT("o1", position=(length, 0), direction=0,
              width=body_w, route_profile=silc_strip))

chip.Route(cpl.ports["o1"], chip.ports["out"])

@lm.pcell
def MZI(length: float = 200, width: float = 0.5):
    c = lm.CELL("MZI")
    splitter = c.add(YSplitter(width=width))
    combiner = c.add(YSplitter(width=width))
    c.Place(splitter).at((0, 0))
    c.Place(combiner).at((length + 60, 0)).rotate_by(180)

    # Re-publish splitter's input as MZI's input.
    splitter.promote(ports=["i1"])
    # Re-publish combiner's input as MZI's output, with a renamed key.
    combiner.promote(ports={"i1": "o1"})

    return c